\doxysection{SPDIFRX\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_s_p_d_i_f_r_x___type_def}{}\label{struct_s_p_d_i_f_r_x___type_def}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}


SPDIF-\/\+RX Interface.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_af97c3ae3a1ced6864b75ee530d96e2d7}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_a215b72b46132acd63634cd950c1f81c4}{IMR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_ad3ff338b3b53a2d26d0154b0037e2a20}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_a380aef459d7c44683aae4cd6e9710a7d}{IFCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_aaffe413c3f6f3153b8b0b953df96e924}{DR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_a8d811e4f5a16f36d6cb45d1369eec51b}{CSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_a76f50bd37d940fd507da3fec5326c96a}{DIR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_p_d_i_f_r_x___type_def_a50425a2dba4883cf40f1f16805daa8e9}{RESERVED2}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
SPDIF-\/\+RX Interface. 

\label{doc-variable-members}
\Hypertarget{struct_s_p_d_i_f_r_x___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_p_d_i_f_r_x___type_def_af97c3ae3a1ced6864b75ee530d96e2d7}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!CR@{CR}}
\index{CR@{CR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_af97c3ae3a1ced6864b75ee530d96e2d7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+CR}

Control register, Address offset\+: 0x00 \Hypertarget{struct_s_p_d_i_f_r_x___type_def_a8d811e4f5a16f36d6cb45d1369eec51b}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_a8d811e4f5a16f36d6cb45d1369eec51b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+CSR}

Channel Status register, Address offset\+: 0x14 \Hypertarget{struct_s_p_d_i_f_r_x___type_def_a76f50bd37d940fd507da3fec5326c96a}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!DIR@{DIR}}
\index{DIR@{DIR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DIR}{DIR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_a76f50bd37d940fd507da3fec5326c96a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+DIR}

Debug Information register, Address offset\+: 0x18 \Hypertarget{struct_s_p_d_i_f_r_x___type_def_aaffe413c3f6f3153b8b0b953df96e924}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!DR@{DR}}
\index{DR@{DR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_aaffe413c3f6f3153b8b0b953df96e924} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+DR}

Data input register, Address offset\+: 0x10 \Hypertarget{struct_s_p_d_i_f_r_x___type_def_a380aef459d7c44683aae4cd6e9710a7d}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!IFCR@{IFCR}}
\index{IFCR@{IFCR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IFCR}{IFCR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_a380aef459d7c44683aae4cd6e9710a7d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+IFCR}

Interrupt Flag Clear register, Address offset\+: 0x0C \Hypertarget{struct_s_p_d_i_f_r_x___type_def_a215b72b46132acd63634cd950c1f81c4}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!IMR@{IMR}}
\index{IMR@{IMR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR}{IMR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_a215b72b46132acd63634cd950c1f81c4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+IMR}

Interrupt mask register, Address offset\+: 0x04 \Hypertarget{struct_s_p_d_i_f_r_x___type_def_a50425a2dba4883cf40f1f16805daa8e9}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_a50425a2dba4883cf40f1f16805daa8e9} 
uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+RESERVED2}

Reserved, 0x1A \Hypertarget{struct_s_p_d_i_f_r_x___type_def_ad3ff338b3b53a2d26d0154b0037e2a20}\index{SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}!SR@{SR}}
\index{SR@{SR}!SPDIFRX\_TypeDef@{SPDIFRX\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_s_p_d_i_f_r_x___type_def_ad3ff338b3b53a2d26d0154b0037e2a20} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SPDIFRX\+\_\+\+Type\+Def\+::\+SR}

Status register, Address offset\+: 0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
